With continuous development of semiconductor technology, semiconductor technology nodes continue to decrease based on Moore's Law. In order to adapt to the reduced technology nodes, channel length of MOSFET devices is shortened. The shortened channel length may allow increases of die density and increases of switching speed of the MOSFET.
However, as the channel length of the device is shortened, the distance between the source and the drain of the device may also be shortened. This increases difficulties for the gate to control the channel region and increases difficulties in gate voltage to pinch off the channel. Then, subthreshold leakage phenomenon, i.e., the so-called short-channel effects, may be more likely to occur.
In order to better adapt to the scaled-down device dimensions, focuses of semiconductor technology are gradually changed from planar MOSFET transistors to three-dimensional-type transistors, such as fin field effect transistor (FinFET), with high efficacy. In a FinFET device, the gate may control the fin at least from both sides of the ultra-thin body (the fin) and may have much stronger control capability on the channel region, as compared with planar MOSFET devices. The short channel effects may be suppressed. Further, the FinFET may have better compatibility with existing IC production technology.
According to carrier mobility enhancement technology, the improved carrier mobility in the channel region may increase drive current of the FinFET device. Performance of FinFET may be improved.
In conventional semiconductor fabrication process, because a stress layer may be used to exert stress in the channel region to alter energy gap and carrier mobility of the silicon material. Performance of FinFET devices may then be improved. In particular, by appropriately controlling the stress in the devices, carrier (e.g., electrons for NMOS FinFET and holes for PMOS FinFET) mobility can be increased to improve drive current to greatly improve the performance of the FinFET devices.
However, the stress layer formed using conventional methods may result in undesirable electrical performance of the resultant FinFET devices.